Pearl Drum-x logic info
|4||bit 1||via diode|
|5||trig||positive pulse to change. has 33k to gnd|
Pin numbera asre according to this Wikipedia article
pull up bits binary to 5v and trigger with pin 5 to 5v to change
the settings are refreshed every 1333,5 us per channel. that is for 8 parameters.
5114 pinout and signals
d7-d9 are the memory addresses for the programs.
0x00 = program 8. 0x01 is program 1 and up.
d0-d6 are the value addresses. clock period 86us. 11.6Khz
bit 2 is not used on the ram chip. 4 clock cycles are used for a analog conversion. so every data value of two niblles are actually read twice before the next one.
Value data pins
two succeeding nibbles form a value. 4 address cycles used per analog value due to the way the DA converter works.
Uses front panel mapping to the address byte. signal duration same as d0. So first parameter of first voice is on d0-d6 all zeroes.
4051 voice parameter decoding address selector pins
!EN is different for each of the five 4051 chips and gets a pulsetrain to mask the wrong values during DA conversion.
The 4040 12bit binary counter is reset every 160 counts of count output d0.
|4040 rst||6.94ms||short pulse|
Signal D0 is the fastest address bit on the memory chip. D1 the second and it is 4 times as slow, not two. every used memory location is read twice.
Signal _WE is the write data pulse. two pulses for both D0 and D4 are shown of data line IO1.
Signal IO1 are the two data bits written. bit0(low) and bit4(hig) the data is shown twice: the first one is the write cycle, the second a read.
sln (set low nibble) is activated for 4 data lines io1-io4 with the 4016 chip just above the sram chip socket. all switch pins are connected to each other and feed with a injection pulse from the 4081 chip top right.
shn (set High Nibble) only sets io1 with bit 4 during the second phase of clock pulse by the 4016 chip top second row just below the two SRAM chip select suppress transistors. incoming data D0 is on pin 11, injection pulse on pin 12.
the injection pulses are in perfect sync with the |WE pulses on the SRAM chip.