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Pearl Drum-x logic info

Drum-x_Da_Converter

ext. trig

mini-din5 pin signal
1 Snare
2 Base
3 Tom3
4 Tom2
5 Tom1
shield GND


Kit select

mini-din5 pin signal comment
1 bit0 via diode
2 bit2 via diode
3 5v -
4 bit 1 via diode
5 trig positive pulse to change. has 33k to gnd
shield GND

Pin numbera asre according to this Wikipedia article

pull up bits binary to 5v and trigger with pin 5 to 5v to change

Value Processing

the settings are refreshed every 1333,5 us per channel. that is for 8 parameters.

5114 pinout and signals

Program addresses

d7-d9 are the memory addresses for the programs.

Pin signal
d7 bit 0
d8 bit 1
d9 bit 2

0x00 = program 8. 0x01 is program 1 and up.


Data Addresses

d0-d6 are the value addresses. clock period 86us. 11.6Khz

bit 2 is not used on the ram chip. 4 clock cycles are used for a analog conversion. so every data value of two niblles are actually read twice before the next one.

bit signal pin
b0 A3 4
b2 A0 5
b3 A1 6
b4 A2 7
b5 A4 3
b6 A5 2
b7 A6 1

Value data pins

two succeeding nibbles form a value. 4 address cycles used per analog value due to the way the DA converter works.


bit 5114 pin
b0 IO1
b1 IO2
b2 IO4
b3 IO3

analog mapping

Uses front panel mapping to the address byte. signal duration same as d0. So first parameter of first voice is on d0-d6 all zeroes.


4051 voice parameter decoding address selector pins

Bit 4051 pin
b0 11
b1 10
b2 9


!EN is different for each of the five 4051 chips and gets a pulsetrain to mask the wrong values during DA conversion.

4051 Enable signal

Timing

The 4040 12bit binary counter is reset every 160 counts of count output d0.

timing:

signal on time comment
4040 d0 43µs blockwave
4040 rst 6.94ms short pulse

4040 reset timing


Writing

Drum-x 4040 write timing.png

Signal D0 is the fastest address bit on the memory chip. D1 the second and it is 4 times as slow, not two. every used memory location is read twice.

Signal _WE is the write data pulse. two pulses for both D0 and D4 are shown of data line IO1.

Signal IO1 are the two data bits written. bit0(low) and bit4(hig) the data is shown twice: the first one is the write cycle, the second a read.

sln (set low nibble) is activated for 4 data lines io1-io4 with the 4016 chip just above the sram chip socket. all switch pins are connected to each other and feed with a injection pulse from the 4081 chip top right.

shn (set High Nibble) only sets io1 with bit 4 during the second phase of clock pulse by the 4016 chip top second row just below the two SRAM chip select suppress transistors. incoming data D0 is on pin 11, injection pulse on pin 12.

the injection pulses are in perfect sync with the |WE pulses on the SRAM chip.